SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this register will reset the associated ring to clear the occupancies and reset the pointers.
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| Instance Name | Physical Address |
|---|---|
| DMASS0_BCDMA_0 | 4860 0040h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ADDR_LO | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ADDR_LO | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADDR_LO | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDR_LO | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | ADDR_LO | R/W | 0h | Ring base address (LSBs) Reset Source: rst_mod_g_rst_n |