SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register provides a writable address which allows debug information to be read from the Debug Data Register
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| Instance Name | Physical Address |
|---|---|
| DMASS0_BCDMA_0 | 485C 0178h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DBG_EN | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DBG_UNIT | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DBG_ADDR | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | DBG_EN | R/W | 0h | Debug enable Reset Source: rst_mod_g_rst_n |
| 30:16 | RESERVED | NONE | 0h | Reserved |
| 15:8 | DBG_UNIT | R/W | 0h | Selects which unit to read debug information from Reset Source: rst_mod_g_rst_n |
| 7:0 | DBG_ADDR | R/W | 0h | Selects offset within unit to access seperate debug registers Reset Source: rst_mod_g_rst_n |