SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register enables or inhibits automatic clock gating to individual sub-blocks
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| Instance Name | Physical Address |
|---|---|
| DMASS0_BCDMA_0 | 485C 0160h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| NOGATE_RSVD4 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| NOGATE_RSVD4 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| NOGATE_RSVD4 | NOGATE_RDEC2 | NOGATE_RSVD3 | NOGATE_SDEC3 | NOGATE_RSVD2 | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NOGATE_WARB3 | NOGATE_RSVD1 | NOGATE_CARB3 | NOGATE_CARB2 | NOGATE_RSVD0 | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:15 | NOGATE_RSVD4 | R/W | 0h | Reserved PM signals. Reset Source: rst_mod_g_rst_n |
| 14 | NOGATE_RDEC2 | R/W | 0h | When set inhibits automatic gating of clock. Reset Source: rst_mod_g_rst_n |
| 13:12 | NOGATE_RSVD3 | R/W | 0h | Reserved PM signals. Reset Source: rst_mod_g_rst_n |
| 11 | NOGATE_SDEC3 | R/W | 0h | When set inhibits automatic gating of clock. Reset Source: rst_mod_g_rst_n |
| 10:8 | NOGATE_RSVD2 | R/W | 0h | Reserved PM signals. Reset Source: rst_mod_g_rst_n |
| 7 | NOGATE_WARB3 | R/W | 0h | When set inhibits automatic gating of clock. Reset Source: rst_mod_g_rst_n |
| 6:4 | NOGATE_RSVD1 | R/W | 0h | Reserved PM signals. Reset Source: rst_mod_g_rst_n |
| 3 | NOGATE_CARB3 | R/W | 0h | When set inhibits automatic gating of clock. Reset Source: rst_mod_g_rst_n |
| 2 | NOGATE_CARB2 | R/W | 0h | When set inhibits automatic gating of clock. Reset Source: rst_mod_g_rst_n |
| 1:0 | NOGATE_RSVD0 | R/W | 0h | Reserved PM signals. Reset Source: rst_mod_g_rst_n |