SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Integration Test Control Register 2.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| DEBUGSS_WRAP0 | 0007 6000 5EF0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | AFVALID | ATREADY | ||||
| R | NONE | R/W | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED | R | 0h | Reserved, returns 0 |
| 3:2 | RESERVED | NONE | 0h | Reserved |
| 1 | AFVALID | R/W | 0h | Reading this bit returns the value of AFVALIDM Writing this bit sets the AFVALIDS[n] bit where n is enabled by the CSTFCTLREG |
| 0 | ATREADY | R/W | 0h | Reading this bit returns the value of ATREADYM Writing this bit sets the AFREADYS[n] bit where n is enabled by the CSTFCTLREG |