SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register displays the supported patterns and modes for calibration
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| Instance Name | Physical Address |
|---|---|
| DEBUGSS_WRAP0 | 0007 6000 4200h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | MODE | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED1 | PATTERN | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:18 | RESERVED | R | 0h | Reserved, returns 0 |
| 17:16 | MODE | R | 0h | bit 16 is Timed Mode, bit 17 is continuous mode |
| 15:4 | RESERVED1 | R | 0h | Reserved, returns 0 |
| 3:0 | PATTERN | R | 0h | bit0=Walking 1 pattern, bit1=walking 0, bit2=AA/55 pattern, bit3=FF/00 pattern |