SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register indicates the implemented Trigger Counter multipliers and other supported features of the trigger system
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| Instance Name | Physical Address |
|---|---|
| DEBUGSS_WRAP0 | 0007 6000 4100h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | TRGRUN | TRIGGERED | |||||
| R | R | R | |||||
| 0h | 0h | 0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED2 | TCOUNT8 | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED1 | MUILTPLIERS | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:18 | RESERVED | R | 0h | Reserved, returns 0 |
| 17 | TRGRUN | R | 0h | Trigger Counter running. A trigger has occurred but the counter is not at zero. |
| 16 | TRIGGERED | R | 0h | A trigger has occurred and the counter has reached zero. |
| 15:9 | RESERVED2 | R | 0h | Reserved, returns 0 |
| 8 | TCOUNT8 | R | 0h | An 8-bit wide counter register implemented. |
| 7:5 | RESERVED1 | R | 0h | Reserved, returns 0 |
| 4:0 | MUILTPLIERS | R | 0h | Multiply the Trigger Counter by 2, 4, 16, 256, 64K supported. Each bit is a mpy value. |