SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This is the control/status register
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| Instance Name | Physical Address |
|---|---|
| DEBUGSS_WRAP0 | 0007 0000 2200h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DBGSWEN | TYPEEXT | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SPIDEN | RESERVED2 | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TYPE | MODE | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TRINPROG | RESERVED1 | ADDR_INC | RESERVED0 | SIZE | |||
| R | R | R/W | R | R | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | DBGSWEN | R/W | 0h | Indicates whether accesses should treated as application or debug |
| 30:24 | TYPEEXT | R/W | 0h | |
| 23 | SPIDEN | R | 0h | When 1, secure accesses are enabled |
| 22:16 | RESERVED2 | R | 0h | Reserved, reads return 0 |
| 15:12 | TYPE | R/W | 0h | Sets Prot, Type attributes for the access |
| 11:8 | MODE | R/W | 0h | Sets mode of operation 0000=basic, 0001=Barrier extensions, all other values reserved |
| 7 | TRINPROG | R | 0h | This bit is set to 1 while a transfer is in progress on the connection to the memory system, and is set to 0 while the connection is idle |
| 6 | RESERVED1 | R | 0h | This bit is reserved and reads return 0 |
| 5:4 | ADDR_INC | R/W | 0h | Address Auto Increment and packing mode |
| 3 | RESERVED0 | R | 0h | reserved, returns 0 |
| 2:0 | SIZE | R | 0h | This specifies the size of the access For this implementation, the access is always 32 bits [010] |