SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
rom table manual entry 54
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| Instance Name | Physical Address |
|---|---|
| DEBUGSS_WRAP0 | 0007 0000 00E0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RA00 | BASEADDR | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| BASEADDR | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| BASEADDR | RA30 | PWRID | |||||
| R | R | R | |||||
| 0h | 0h | 1h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PWRID | RA0 | PWRIDVAL | RA1 | RESERVED | |||
| R | R | R | R | NONE | |||
| 1h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RA00 | R | 0h | always read as 0 |
| 30:12 | BASEADDR | R | 0h | Component base address |
| 11:9 | RA30 | R | 0h | always read as 0 |
| 8:4 | PWRID | R | 1h | always read as 0 |
| 3 | RA0 | R | 0h | always read as 0 |
| 2 | PWRIDVAL | R | 0h | power id valid |
| 1 | RA1 | R | 0h | always read as 1 |
| 0 | RESERVED | NONE | 0h | Reserved |