SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Starts / stops the counters. Clears the error signal.
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| Instance Name | Physical Address |
|---|---|
| DCC0 | 0080 0000h |
| DCC1 | 0080 4000h |
| DCC2 | 0080 8000h |
| DCC3 | 0080 C000h |
| DCC4 | 0081 0000h |
| DCC5 | 0081 4000h |
| DCC6 | 0081 8000h |
| DCC7 | 0081 C000h |
| DCC8 | 0082 0000h |
| MCU_DCC0 | 04C0 0000h |
| MCU_DCC1 | 04C1 0000h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DONEENA | SINGLESHOT | ||||||
| R/W | R/W | ||||||
| 5h | 5h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ERRENA | DCCENA | ||||||
| R/W | R/W | ||||||
| 5h | 5h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15:12 | DONEENA | R/W | 5h | The DONEENA bit enables/disables the done interrupt signal, but has no effect on the done status flag in DCCSTAT register. User, privilege, and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege and debug mode (write): 0101 = disable done signal generation others = enable done signal generation |
| 11:8 | SINGLESHOT | R/W | 5h | The SINGLESHOT bit enables/disables repetitive operation of the DCC. User, privilege, and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously repeat (until error) Privilege and debug mode (write): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously repeat (until error) |
| 7:4 | ERRENA | R/W | 5h | The ERRENA bit enables/disables the error signal. User, privilege, and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others = enable error signal generation |
| 3:0 | DCCENA | R/W | 5h | The DCCENA bit starts and stops the operation of the dcc. User, privilege, and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the counters with their seed values and begin counting |