SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Time Sync Control Register
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0803 D004h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| TS_SYNC_SEL | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | TS_GENF_CLR_EN | TS_RX_NO_EVENT | |||||
| NONE | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| HW8_TS_PUSH_EN | HW7_TS_PUSH_EN | HW6_TS_PUSH_EN | HW5_TS_PUSH_EN | HW4_TS_PUSH_EN | HW3_TS_PUSH_EN | HW2_TS_PUSH_EN | HW1_TS_PUSH_EN |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TS_PPM_DIR | TS_COMP_TOG | MODE | SEQUENCE_EN | TSTAMP_EN | TS_COMP_POLARITY | INT_TEST | CPTS_EN |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 1h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | TS_SYNC_SEL | R/W | 0h | TS_SYNC output time stamp counter bit select. 0h TS_SYNC disabled.
1h-Fh TS_SYNC is time stamp counter bits 31 (Fh)
down to 17 (1h). |
| 27:18 | RESERVED | NONE | 0h | Reserved |
| 17 | TS_GENF_CLR_EN | R/W | 0h | GENF (and ESTF) Clear Enable. 0h A CPTS_GENFn output is not cleared when the
associated CPSW_GENF_LENGTH_REG_l[31:0] is
cleared to zero.
1h A CPTS_GENFn output is cleared when the
associated CPSW_GENF_LENGTH_REG_l[31:0] is
cleared to zero. |
| 16 | TS_RX_NO_EVENT | R/W | 0h | Timestamp Ethernet Receive produces no events. 0h Ethernet receive timesync events enabled. 1h Ethernet receive timesync events disabled. |
| 15 | HW8_TS_PUSH_EN | R/W | 0h | Hardware push 8 enable. |
| 14 | HW7_TS_PUSH_EN | R/W | 0h | Hardware push 7 enable. |
| 13 | HW6_TS_PUSH_EN | R/W | 0h | Hardware push 6 enable. |
| 12 | HW5_TS_PUSH_EN | R/W | 0h | Hardware push 5 enable. |
| 11 | HW4_TS_PUSH_EN | R/W | 0h | Hardware push 4 enable. |
| 10 | HW3_TS_PUSH_EN | R/W | 0h | Hardware push 3 enable. |
| 9 | HW2_TS_PUSH_EN | R/W | 0h | Hardware push 2 enable. |
| 8 | HW1_TS_PUSH_EN | R/W | 0h | Hardware push 1 enable. |
| 7 | TS_PPM_DIR | R/W | 0h | PPM Correction Direction. 0h Increase the TIME_STAMP[63:0] value
(CPSW_CPTS_EVENT_0_REG and
CPSW_CPTS_EVENT_3_REG) by the PPM value.
1h Decrease the TIME_STAMP[63:0] value
(CPSW_CPTS_EVENT_0_REG and
CPSW_CPTS_EVENT_3_REG and) by the PPM
value. |
| 6 | TS_COMP_TOG | R/W | 0h | Time Stamp Compare Toggle mode. 0h TS_COMP is in non-toggle mode. 1h TS_COMP is in toggle mode. |
| 5 | MODE | R/W | 0h | 64-Bit Mode. 0h The time stamp is 32-bits with the upper
32-bits forced to zero.
1h The time stamp is 64-bits. |
| 4 | SEQUENCE_EN | R/W | 0h | Sequence Enable. 0h The time stamp value increments with the
selected RFTCLK
1h The time stamp for received packets is the
sequence number of the received packet
(first packet is 1, second packet is 2,
etc). |
| 3 | TSTAMP_EN | R/W | 0h | Host Receive Time Stamp Enable. 0h Time stamps are disabled on received
packets to host.
1h Time stamps enabled on received packets to
host (PCIE_CPTS_CONTROL_REG[0] CPTS_EN must
be set). |
| 2 | TS_COMP_POLARITY | R/W | 1h | TS_COMP Polarity. 0h TS_COMP is asserted low. 1h TS_COMP is asserted high. |
| 1 | INT_TEST | R/W | 0h | Interrupt Test. When set, this bit allows the raw interrupt to be written to facilitate interrupt test. |
| 0 | CPTS_EN | R/W | 0h | Time Sync Enable. When disabled (cleared to zero), the RCLK domain is held in reset. |