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SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1

14.7.3.1.2.181 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_EST_CONTROL_REG Register

1.2.181.1 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_EST_CONTROL_REG Register (Offset = 23060h) [reset = 0h]

Enet Port N EST CONTROL

Table 14-12261 Instance Table

Instance Name	Physical Address
CPSW0	0802 3060h + formula

Figure 14-6072 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_EST_CONTROL_REG Name Register

31	30	29	28	27	26	25	24
RESERVED						EST_FILL_MARGIN
NONE						R/W
0h						0h
23	22	21	20	19	18	17	16
EST_FILL_MARGIN
R/W
0h
15	14	13	12	11	10	9	8
EST_PREMPT_COMP							EST_FILL_EN
R/W							R/W
0h							0h
7	6	5	4	3	2	1	0
EST_TS_PRI			EST_TS_ONEPRI	EST_TS_FIRST	EST_TS_EN	EST_BUFSEL	EST_ONEBUF
R/W			R/W	R/W	R/W	R/W	R/W
0h			0h	0h	0h	0h	0h

Table 14-12262 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_EST_CONTROL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31:26	RESERVED	NONE	0h	Reserved
25:16	EST_FILL_MARGIN	R/W	0h	EST Fill Margin. Sets the fill margin required to ensure that the Ethernet wire is clear (including IPG) so that the timed EST express packet can egress at the required time. Setting this value too high will put an unnecessary gap on the wire. Setting this value too low will cause the express packet to egress at a time later than intended.
15:9	EST_PREMPT_COMP	R/W	0h	EST Prempt Comparison Value. When the count in a zero allow is less than or equal to this value in bytes (times 8), prempt packets are cleared from the wire. This is the prempt clear margin value.
8	EST_FILL_EN	R/W	0h	EST Fill Enable. Enable EST fill mode.
7:5	EST_TS_PRI	R/W	0h	EST Timestamp Express Priority. Selects the express priority that timestamp(s) will be generated on when CPSW_PN_EST_CONTROL_REG_k[4] EST_TS_ONEPRI bit is set.
4	EST_TS_ONEPRI	R/W	0h	EST Timestamp One Express Priority. When set, timestamp only enabled packets on the express priority selected by CPSW_PN_EST_CONTROL_REG_k[7-5] ST_TS_PRI bit field. When cleared to zero, express packet selection for timestamp is independent of priority.
3	EST_TS_FIRST	R/W	0h	EST Timestamp First Express Packet only. Generate a timestamp only on the first selected express packet in each EST time interval when express timestamps are enabled. (If CPSW_PN_EST_CONTROL_REG_k[4] EST_TS_ONEPRI is also set then the timestamp is generated only on the first packet on CPSW_PN_EST_CONTROL_REG_k[7-5] ST_TS_PRI).
2	EST_TS_EN	R/W	0h	EST Timestamp Enable. Enable express timestamps (when CPSW_CONTROL_REG[18] EST_ENABLE and CPSW_PN_CONTROL_REG_k[17] EST_PORT_EN bits are set).
1	EST_BUFSEL	R/W	0h	EST Buffer Select. If CPSW_PN_EST_CONTROL_REG_k[0] EST_ONEBUF is cleared, this bit selects the upper (when set) or the lower (when cleared) 64-word fetch buffer. The actual fetch buffer used changes only at the start of the EST time interval and can be read in the CPSW_PN_FIFO_STATUS_REG_k register, bit [18] EST_BUFACT.
0	EST_ONEBUF	R/W	0h	EST One Fetch Buffer. When set indicates that all 128 fetch words are used in one buffer. When cleared, indicates that the 128 fetch words are split into two 64-word fetch buffers. The CPSW_PN_EST_CONTROL_REG_k[1] EST_BUFSEL bit selects the buffer to be used when bit [0] EST_ONEBUF is cleared to zero.