SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Enet Port N FIFO Max Blocks
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0802 3008h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TX_MAX_BLKS | |||||||
| R/W | |||||||
| 10h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RX_MAX_BLKS | |||||||
| R/W | |||||||
| 4h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15:8 | TX_MAX_BLKS | R/W | 10h | Transmit Max Blocks. The maximum number of blocks allowed on all transmit FIFO priorities combined. If (fifo_oneram = 1) then blocks should be moved from transmit to receive, when Fullduplex flow control is enabled (CPSW_PN_MAC_CONTROL_REG_k[0] FULLDUPLEX = 1h) to allow for flow control runout. |
| 7:0 | RX_MAX_BLKS | R/W | 4h | Receive Max Blocks. The maximum number of blocks allowed on the express and prempt receive FIFOs (transmit and receive FIFO's combined when fifo_oneram = 1) |