SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Enet Port N Mac Control
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0802 2330h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | RX_CMF_EN | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RX_CSF_EN | RX_CEF_EN | TX_SHORT_GAP_LIM_EN | EXT_TX_FLOW_EN | EXT_RX_FLOW_EN | EXT_EN | GIG_FORCE | |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| IFCTL_A | RESERVED | CRC_TYPE | CMD_IDLE | TX_SHORT_GAP_ENABLE | RESERVED | ||
| R/W | NONE | R/W | R/W | R/W | NONE | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GIG | TX_PACE | GMII_EN | TX_FLOW_EN | RX_FLOW_EN | MTEST | LOOPBACK | FULLDUPLEX |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RESERVED | NONE | 0h | Reserved |
| 24 | RX_CMF_EN | R/W | 0h | RX Copy MAC Control Frames Enable. Enables MAC control frames to be transferred to memory. MAC control frames are normally acted upon (if enabled), but not copied to memory. MAC control frames that are pause frames will be acted upon if enabled in the CPSW_PN_MAC_CONTROL_REG_k register, regardless of the value of [24] RX_CMF_EN bit. Frames transferred to memory due to [24] RX_CMF_EN will have the control bit set in their EOP buffer descriptor. 0h MAC control frames are filtered (but acted
upon if enabled).
1h MAC control frames are transferred to
memory. |
| 23 | RX_CSF_EN | R/W | 0h | RX Copy Short Frames Enable. Enables frames or fragments shorter than 64 bytes to be copied to memory. Frames transferred to memory due to CPSW_PN_MAC_CONTROL_REG_k[23] RX_CSF_EN will have the fragment or undersized bit set in their receive footer. Fragments are short frames that contain CRC/align/code errors and undersized are short frames without errors. 0h Short frames are filtered. 1h Short frames are transferred to memory. |
| 22 | RX_CEF_EN | R/W | 0h | RX Copy Error Frames Enable. Enables frames containing errors to be transferred to memory. The appropriate error bit will be set in the frame receive footer. Frames containing errors will be filtered when CPSW_PN_MAC_CONTROL_REG_k[22] RX_CEF_EN is not set. 0h Frames containing errors are filtered.
1h Frames containing errors are transferred to
memory. |
| 21 | TX_SHORT_GAP_LIM_EN | R/W | 0h | Transmit Short Gap Limit Enable When set this bit limits the number of short gap packets transmitted to 100ppm. The TX_SHORT_GAP_ENABLE bit must also be set. Each time a short gap packet is sent, a counter is loaded with 10,000 and decremented on each wireside clock. Another short gap packet will not be sent out until the counter decrements to zero. This mode is included to preclude the host from filling up the FIFO and sending every packet out with short gap which would violate the maximum number of packets per second allowed. This bit is used only with GMII (not XGMII). |
| 20 | EXT_TX_FLOW_EN | R/W | 0h | External Transmit Flow Control Enable. Enables the TX_FLOW_EN to be selected from the EXT_TX_FLOW_EN input signal and not from the [4] TX_FLOW_EN bit in CPSW_PN_MAC_CONTROL_REG_k register. |
| 19 | EXT_RX_FLOW_EN | R/W | 0h | External Receive Flow Control Enable. Enables the RX_FLOW_EN to be selected from the EXT_RX_FLOW_EN input signal and not from the CPSW_PN_MAC_CONTROL_REG_k[3] RX_FLOW_EN bit in this register. |
| 18 | EXT_EN | R/W | 0h | External Control Enable. Enables the fullduplex and gigabit mode to be selected from the FULLDUPLEX_IN and GIG_IN input signals and not from the [0] FULLDUPLEX and [7] GIG bits in the CPSW_PN_MAC_CONTROL_REG_k register. The [0] FULLDUPLEX bit reflects the actual fullduplex mode selected. |
| 17 | GIG_FORCE | R/W | 0h | Gigabit Mode Force. This bit is used to force the Ethernet Mac into gigabit mode if the input GMII_MTCLK has been stopped by the PHY. |
| 15 | IFCTL_A | R/W | 0h | Determines the RMII link speed. 0h 10Mbps operation 0h 100Mbps operation |
| 14:13 | RESERVED | NONE | 0h | Reserved |
| 12 | CRC_TYPE | R/W | 0h | Port CRC Type. 0h Ethernet CRC 1h Castagnoli CRC |
| 11 | CMD_IDLE | R/W | 0h | Command Idle. 0h Idle not commanded
1h Idle Commanded (read bit [31] IDLE in
CPSW_PN_MAC_STATUS_REG_k register) |
| 10 | TX_SHORT_GAP_ENABLE | R/W | 0h | Transmit Short Gap Enable. 0h Transmit with a short IPG is disabled
1h Transmit with a short IPG (when
TX_SHORT_GAP input is asserted) is enabled. |
| 9:8 | RESERVED | NONE | 0h | Reserved |
| 7 | GIG | R/W | 0h | Gigabit Mode. 0h 10/100 mode
1h Gigabit mode (full duplex only) The GIG_OUT
output is the value of this bit. |
| 6 | TX_PACE | R/W | 0h | Transmit Pacing Enable 0h Transmit Pacing Disabled 1h Transmit Pacing Enabled |
| 5 | GMII_EN | R/W | 0h | GMII Enable. 0h GMII RX and TX held in reset. 1h GMII RX and TX released from reset. |
| 4 | TX_FLOW_EN | R/W | 0h | Transmit Flow Control Enable. Determines if incoming pause frames are acted upon in full-duplex mode. Incoming pause frames are not acted upon in half-duplex mode regardless of this bit setting. The RX_MBP_ENABLE bits determine whether or not received pause frames are transferred to memory. 0h Transmit Flow Control Disabled. Full-duplex
mode - Incoming pause frames are not acted
upon.
1h Transmit Flow Control Enabled. Full-duplex
mode - Incoming pause frames are acted
upon. |
| 3 | RX_FLOW_EN | R/W | 0h | Receive Flow Control Enable. 0h Receive Flow Control Disabled Half-duplex
mode - No flow control generated collisions
are sent. Full-duplex mode - No outgoing
pause frames are sent.
1h Receive Flow Control Enabled Half-duplex
mode - Collisions are initiated when
receive flow control is triggered. Full-
duplex mode - Outgoing pause frames are
sent when receive flow control is
triggered. |
| 2 | MTEST | R/W | 0h | Manufacturing Test mode. This bit must be set to allow writes to the CPSW_PN_MAC_BOFFTEST_REG_k and CPSW_PN_MAC_RX_PAUSETIMER_REG_k registers. |
| 1 | LOOPBACK | R/W | 0h | Loop Back Mode. Loopback mode forces internal fullduplex mode regardless of whether the CPSW_PN_MAC_CONTROL_REG_k[0] FULLDUPLEX bit is set or not. The [1] LOOPBACK bit should be changed only when [5] GMII_EN is de-asserted. Loopback is used only with GMII (not XGMII). Loopback is not compatible with timestamp operations (CPTS). 0h Not looped back mode 1h Loop Back mode enabled |
| 0 | FULLDUPLEX | R/W | 0h | Full Duplex mode. Gigabit mode forces fullduplex mode regardless of whether the [0] FULLDUPLEX bit is set or not. The FULLDUPLEX_OUT output is the value of this register bit 0h Half duplex mode 1h Full duplex mode |