SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Port 0 EEE status
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0802 1038h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TX_FIFO_EMPTY | RX_FIFO_EMPTY | TX_FIFO_HOLD | TX_WAKE | TX_LPI | RX_LPI | WAIT_IDLE2LPI |
| NONE | R | R | R | R | R | R | R |
| 0h | 1h | 1h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:7 | RESERVED | NONE | 0h | Reserved |
| 6 | TX_FIFO_EMPTY | R | 1h | CPPI port 0 transmit FIFO (switch egress) is empty - contains no packets |
| 5 | RX_FIFO_EMPTY | R | 1h | CPPI port 0 receive FIFO (switch ingress) is empty - contains no packets |
| 4 | TX_FIFO_HOLD | R | 0h | CPPI port 0 transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time |
| 3 | TX_WAKE | R | 0h | CPPI port 0 transmit wakeup - asserted in the transmit LPI2WAKE count time |
| 2 | TX_LPI | R | 0h | CPPI port 0 transmit LPI state - asserted when the port 0 transmit is in the LPI state |
| 1 | RX_LPI | R | 0h | CPPI port 0 receive LPI state - asserted when the port 0 receive is in the LPI state |
| 0 | WAIT_IDLE2LPI | R | 0h | CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time |