SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
MDIO Alive Register
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0800 0F08h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ALIVE | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ALIVE | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ALIVE | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ALIVE | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | ALIVE | R/W | 0h | MDIO Alive. Each of the 32-bits of this register is set if the most recent access to the PHY with address corresponding to the register bit number was acknowledged by the PHY, the bit is reset if the PHY fails to acknowledge the access. Both the user and polling accesses to a PHY will cause the corresponding alive bit to be updated. The alive bits are intended to be used to give an indication of the presence or not of the PHY with the corresponding address. Writing a 1h to any bit will clear it, writing a 0h has no effect. |