SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The ISC Region 2 Control Register defines the control fields for the initiator Ipulsar_ul_wkup_0.cpu0_pmst region 2 ISC.
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| Instance Name | Physical Address |
|---|---|
| WKUP_CBASS0 | 4581 4040h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | NOPRIV | PRIV | |||||
| NONE | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PASS | NONSEC | SEC | ||||
| NONE | R/W | R/W | R/W | ||||
| 0h | 0h | 1h | 0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PRIV_ID | |||||||
| R/W | |||||||
| D4h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DEF | CH_MODE | LOCK | ENABLE | |||
| NONE | R | R/W | R/W1TS | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | RESERVED | NONE | 0h | Reserved |
| 27:26 | NOPRIV | R/W | 0h | Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared. Reset Source: domain_default_rst_mod_g_rst_n |
| 25:24 | PRIV | R/W | 0h | Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set. Reset Source: domain_default_rst_mod_g_rst_n |
| 23:22 | RESERVED | NONE | 0h | Reserved |
| 21 | PASS | R/W | 0h | No privID replacement, pass through value. Reset Source: domain_default_rst_mod_g_rst_n |
| 20 | NONSEC | R/W | 1h | Make outgoing non-secure. Reset Source: domain_default_rst_mod_g_rst_n |
| 19:16 | SEC | R/W | 0h | Make outgoing secure. A value of 0xA enables, others disable. Reset Source: domain_default_rst_mod_g_rst_n |
| 15:8 | PRIV_ID | R/W | D4h | Priv ID. Reset Source: domain_default_rst_mod_g_rst_n |
| 7 | RESERVED | NONE | 0h | Reserved |
| 6 | DEF | R | 0h | Default region indication. The default region is used when all other regions do not match. Reset Source: domain_default_rst_mod_g_rst_n |
| 5 | CH_MODE | R/W | 0h | Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range. Reset Source: domain_default_rst_mod_g_rst_n |
| 4 | LOCK | R/W1TS | 0h | Lock region. Once set the region values cannot be modified. Reset Source: domain_default_rst_mod_g_rst_n |
| 3:0 | ENABLE | R/W | 0h | Enable region. A value of 0xA enables, others disable. Reset Source: domain_default_rst_mod_g_rst_n |