SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the initiator Ipulsar_ul_wkup_0.cpu0_pmst region 1 ISC.
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| Instance Name | Physical Address |
|---|---|
| WKUP_CBASS0 | 4581 4038h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| END_ADDRESS_L | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| END_ADDRESS_L | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| END_ADDRESS_L | END_ADDRESS_LSB | ||||||
| R/W | R | ||||||
| 0h | FFFh | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| END_ADDRESS_LSB | |||||||
| R | |||||||
| FFFh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:12 | END_ADDRESS_L | R/W | 0h | End address bits 31 to 12 to include in the match. Reset Source: domain_default_rst_mod_g_rst_n |
| 11:0 | END_ADDRESS_LSB | R | FFFh | End address bits 11 to 0 are forced to Fs as address must be 4KB aligned. Reset Source: domain_default_rst_mod_g_rst_n |