SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Configures PRG_PP_1 - Ping-Pong Capable POKs
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| Instance Name | Physical Address |
|---|---|
| MCU_CTRL_MMR0 | 0451 A208h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PRG_PP_1_CTRL_POK_PP_EN_PROXY | RESERVED | PRG_PP_1_CTRL_DEGLITCH_SEL_PROXY | ||||
| NONE | R/W | NONE | R/W | ||||
| 0h | 0h | 0h | 2h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PRG_PP_1_CTRL_POK_EN_SEL_PROXY | PRG_PP_1_CTRL_POK_VDDS_DDRIO_OV_SEL_PROXY | PRG_PP_1_CTRL_POK_VDDSHV_MAIN_3P3_OV_SEL_PROXY | PRG_PP_1_CTRL_POK_VDDSHV_MAIN_1P8_OV_SEL_PROXY | PRG_PP_1_CTRL_POK_VMON_CAP_MCU_GENERAL_OV_SEL_PROXY | PRG_PP_1_CTRL_POK_VDDR_CORE_OV_SEL_PROXY | ||
| R/W | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PRG_PP_1_CTRL_POK_VDDS_DDRIO_EN_PROXY | PRG_PP_1_CTRL_POK_VDDSHV_MAIN_3P3_EN_PROXY | PRG_PP_1_CTRL_POK_VDDSHV_MAIN_1P8_EN_PROXY | PRG_PP_1_CTRL_POK_VMON_CAP_MCU_GENERAL_EN_PROXY | PRG_PP_1_CTRL_POK_VDDR_CORE_EN_PROXY | ||
| NONE | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 1h | 1h | 1h | 1h | 1h | 1h | 1h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:20 | RESERVED | NONE | 0h | Reserved |
| 19 | PRG_PP_1_CTRL_POK_PP_EN_PROXY | R/W | 0h | POK ping-pong enable. When set, POKs with their ov_sel option set to UV_OR_PINGPONG are automatically cycled between UV and OV detection (ping-pong). POKs with ov_sel selecting OV are unaffected by this bit. Field values (others are reserved): 1'b0 - UV_FIXED 1'b1 - UV_PINGPONG_OV Reset Source: mod_por_rst_n |
| 18 | RESERVED | NONE | 0h | Reserved |
| 17:16 | PRG_PP_1_CTRL_DEGLITCH_SEL_PROXY | R/W | 2h | Deglitch period for PRG_PP1 POKs (microseconds) Field values (others are reserved): 2'b00 - DG_5_US 2'b01 - DG_10_US 2'b10 - DG_15_US 2'b11 - DG_20_US Reset Source: mod_por_rst_n |
| 15 | PRG_PP_1_CTRL_POK_EN_SEL_PROXY | R/W | 0h | Selects source of POK controls Field values (others are reserved): 1'b0 - TIEOFFS 1'b1 - PRG_PP0_CTRL_REG Reset Source: mod_por_rst_n |
| 14 | PRG_PP_1_CTRL_POK_VDDS_DDRIO_OV_SEL_PROXY | R/W | 0h | POK_VDDS_DDRIO mode (undervoltage/ping-pong or over-voltage) Field values (others are reserved): 1'b0 - UV_OR_PINGPONG 1'b1 - OV Reset Source: mod_por_rst_n |
| 13 | PRG_PP_1_CTRL_POK_VDDSHV_MAIN_3P3_OV_SEL_PROXY | R/W | 0h | POK_VDDSHV_MAIN_3P3 mode (undervoltage/ping-pong or over-voltage) Field values (others are reserved): 1'b0 - UV_OR_PINGPONG 1'b1 - OV Reset Source: mod_por_rst_n |
| 12 | PRG_PP_1_CTRL_POK_VDDSHV_MAIN_1P8_OV_SEL_PROXY | R/W | 0h | POK_VDDSHV_MAIN_1P8 mode (undervoltage/ping-pong or over-voltage) Field values (others are reserved): 1'b0 - UV_OR_PINGPONG 1'b1 - OV Reset Source: mod_por_rst_n |
| 11 | PRG_PP_1_CTRL_POK_VMON_CAP_MCU_GENERAL_OV_SEL_PROXY | R/W | 0h | POK_VMON_CAP_MCU_GENERAL mode (undervoltage/ping-pong or over-voltage) Field values (others are reserved): 1'b0 - UV_OR_PINGPONG 1'b1 - OV Reset Source: mod_por_rst_n |
| 8 | PRG_PP_1_CTRL_POK_VDDR_CORE_OV_SEL_PROXY | R/W | 0h | POK_VDDR_CORE mode (undervoltage/ping-pong or over-voltage) Field values (others are reserved): 1'b0 - UV_OR_PINGPONG 1'b1 - OV Reset Source: mod_por_rst_n |
| 7 | RESERVED | NONE | 0h | Reserved |
| 6 | PRG_PP_1_CTRL_POK_VDDS_DDRIO_EN_PROXY | R/W | 1h | Enable POK_VDDS_DDRIO (if pok_en_sel = 1): Field values (others are reserved): 1'b0 - Disabled 1'b1 - Enabled Reset Source: mod_por_rst_n |
| 5 | PRG_PP_1_CTRL_POK_VDDSHV_MAIN_3P3_EN_PROXY | R/W | 1h | Enable POK_VDDSHV_MAIN_3P3 (if pok_en_sel = 1): Field values (others are reserved): 1'b0 - Disabled 1'b1 - Enabled Reset Source: mod_por_rst_n |
| 4 | PRG_PP_1_CTRL_POK_VDDSHV_MAIN_1P8_EN_PROXY | R/W | 1h | Enable POK_VDDSHV_MAIN_1P8 (if pok_en_sel = 1): Field values (others are reserved): 1'b0 - Disabled 1'b1 - Enabled Reset Source: mod_por_rst_n |
| 3 | PRG_PP_1_CTRL_POK_VMON_CAP_MCU_GENERAL_EN_PROXY | R/W | 1h | Enable POK_VMON_CAP_MCU_GENERAL (if pok_en_sel = 1): Field values (others are reserved): 1'b0 - Disabled 1'b1 - Enabled Reset Source: mod_por_rst_n |
| 0 | PRG_PP_1_CTRL_POK_VDDR_CORE_EN_PROXY | R/W | 1h | Enable POK_VDDR_CORE (if pok_en_sel = 1): Field values (others are reserved): 1'b0 - Disabled 1'b1 - Enabled Reset Source: mod_por_rst_n |