SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Hysterisis, Threshold, and Control of VDD_CORE Under/Over Voltage Monitors in POR (POKLVB) and POK_VDD_CORE_UV
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MCU_CTRL_MMR0 | 0451 A118h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| POK_VDD_CORE_UV_CTRL_HYST_EN_PROXY | RESERVED | ||||||
| R/W | NONE | ||||||
| 1h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| POK_VDD_CORE_UV_CTRL_OVER_VOLT_DET_PROXY | |||||||
| R/W | |||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | POK_VDD_CORE_UV_CTRL_HYST_EN_PROXY | R/W | 1h | Enable POK hysteresis Field values (others are reserved): 1'b0 - DISABLE 1'b1 - ENABLE Reset Source: mod_por_rst_n |
| 30:8 | RESERVED | NONE | 0h | Reserved |
| 7 | POK_VDD_CORE_UV_CTRL_OVER_VOLT_DET_PROXY | R/W | 0h | Over / under voltage detection mode Field values (others are reserved): 1'b0 - UNDERVOLTAGE_MODE 1'b1 - OVERVOLTAGE_MODE Reset Source: mod_por_rst_n |