SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Configures PRG_PP_0 - Fixed POKs (In POR, POKSA, and POK_VDD_CORE_OV)
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| Instance Name | Physical Address |
|---|---|
| MCU_CTRL_MMR0 | 0451 8200h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PRG_PP_0_CTRL_DEGLITCH_SEL | ||||||
| NONE | R/W | ||||||
| 0h | 2h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PRG_PP_0_CTRL_POK_EN_SEL | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PRG_PP_0_CTRL_POK_VDDA_PMIC_IN_UV_EN | PRG_PP_0_CTRL_POK_VDD_MCU_OV_EN | PRG_PP_0_CTRL_POK_VDD_MCU_UV_EN | PRG_PP_0_CTRL_POK_VDDA_MCU_OV_EN | PRG_PP_0_CTRL_POK_VDDA_MCU_UV_EN | ||
| NONE | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 1h | 1h | 1h | 1h | 1h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:18 | RESERVED | NONE | 0h | Reserved |
| 17:16 | PRG_PP_0_CTRL_DEGLITCH_SEL | R/W | 2h | Deglitch period for PRG_PP1 POKs (microseconds) Field values (others are reserved): 2'b00 - DG_5_US 2'b01 - DG_10_US 2'b10 - DG_15_US 2'b11 - DG_20_US Reset Source: mod_por_rst_n |
| 15 | PRG_PP_0_CTRL_POK_EN_SEL | R/W | 0h | Selects source of POK controls Field values (others are reserved): 1'b0 - TIEOFFS 1'b1 - PRG_PP0_CTRL_REG Reset Source: mod_por_rst_n |
| 14:5 | RESERVED | NONE | 0h | Reserved |
| 4 | PRG_PP_0_CTRL_POK_VDDA_PMIC_IN_UV_EN | R/W | 1h | Enable VDDA_PMIC_IN undervoltage POK detection Field values (others are reserved): 1'b0 - Disabled 1'b1 - Enabled Reset Source: mod_por_rst_n |
| 3 | PRG_PP_0_CTRL_POK_VDD_MCU_OV_EN | R/W | 1h | Enable VDD_MCU overvoltage POK detection Field values (others are reserved): 1'b0 - Disabled 1'b1 - Enabled Reset Source: mod_por_rst_n |
| 2 | PRG_PP_0_CTRL_POK_VDD_MCU_UV_EN | R/W | 1h | Enable VDD_MCU undervoltage POK detection Field values (others are reserved): 1'b0 - Disabled 1'b1 - Enabled Reset Source: mod_por_rst_n |
| 1 | PRG_PP_0_CTRL_POK_VDDA_MCU_OV_EN | R/W | 1h | Enable 1.8V VDDA_MCU overvoltage POK detection Field values (others are reserved): 1'b0 - Disabled 1'b1 - Enabled Reset Source: mod_por_rst_n |
| 0 | PRG_PP_0_CTRL_POK_VDDA_MCU_UV_EN | R/W | 1h | Enable 1.8V VDDA_MCU undervoltage POK detection Field values (others are reserved): 1'b0 - Disabled 1'b1 - Enabled Reset Source: mod_por_rst_n |