SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Shows Cluster Core0 power status
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| Instance Name | Physical Address |
|---|---|
| MAIN_SEC_MMR0 | 45A0 1130h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CLSTR1_CORE0_PMSTAT_CLK_GATE | RESERVED | CLSTR1_CORE0_PMSTAT_WFE | CLSTR1_CORE0_PMSTAT_WFI | |||
| NONE | R | NONE | R | R | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED | NONE | 0h | Reserved |
| 3 | CLSTR1_CORE0_PMSTAT_CLK_GATE | R | 0h | Core0 Clocked stopped due to WFI or WFE state Note: Bit value is invalid when Core0 is in reset Reset Source: mod_g_rst_n |
| 2 | RESERVED | NONE | 0h | Reserved |
| 1 | CLSTR1_CORE0_PMSTAT_WFE | R | 0h | Core0 WFE When 0, indicates that Core0 is in the WFE state Note: Bit value is invalid when Core0 is in reset Reset Source: mod_g_rst_n |
| 0 | CLSTR1_CORE0_PMSTAT_WFI | R | 0h | Core0 WFI When 0, indicates that Core0 is in the WFI state Note: Bit value is invalid when Core0 is in reset Reset Source: mod_g_rst_n |