SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Configures the TCM and interrupt operation of R5 Core1
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| Instance Name | Physical Address |
|---|---|
| MAIN_SEC_MMR0 | 45A0 0180h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CLSTR0_CORE1_CFG_NMFI_EN | RESERVED | CLSTR0_CORE1_CFG_TCM_RSTBASE | RESERVED | ||||
| R/W | NONE | R/W | NONE | ||||
| 0h | 0h | 1h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLSTR0_CORE1_CFG_BTCM_EN | RESERVED | CLSTR0_CORE1_CFG_ATCM_EN | RESERVED | ||||
| R/W | NONE | R/W | NONE | ||||
| 1h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15 | CLSTR0_CORE1_CFG_NMFI_EN | R/W | 0h | Enable Core1 Non-Maskable Fast Interrupts CAUTION: This bit must not be modified if R5F core has been released from reset. Reset Source: sys_por_rst_n |
| 14:12 | RESERVED | NONE | 0h | Reserved |
| 11 | CLSTR0_CORE1_CFG_TCM_RSTBASE | R/W | 1h | Core1 A/BTCM Reset Base Address Indicator 0 - BTCM located at address 0x0 1 - ATCM located at address 0x0 CAUTION: This bit must not be modified if R5F core has been released from reset. Reset Source: sys_por_rst_n |
| 10:8 | RESERVED | NONE | 0h | Reserved |
| 7 | CLSTR0_CORE1_CFG_BTCM_EN | R/W | 1h | Enable Core1 BTCM RAM at reset CAUTION: This bit must not be modified if R5F core has been released from reset. Reset Source: sys_por_rst_n |
| 6:4 | RESERVED | NONE | 0h | Reserved |
| 3 | CLSTR0_CORE1_CFG_ATCM_EN | R/W | 0h | Enable Core1 ATCM RAM at reset CAUTION: This bit must not be modified if R5F core has been released from reset. Reset Source: sys_por_rst_n |
| 2:0 | RESERVED | NONE | 0h | Reserved |