SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Defines the type of the processor cluster
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| Instance Name | Physical Address |
|---|---|
| MAIN_SEC_MMR0 | 45A0 0020h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | CLSTR0_DEF_CORE_NUM | ||||||
| NONE | R | ||||||
| 0h | 2h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CLSTR0_DEF_DSP_CORE_TYPE | |||||||
| R | |||||||
| FFh | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLSTR0_DEF_ARM_CORE_TYPE | |||||||
| R | |||||||
| 10h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:19 | RESERVED | NONE | 0h | Reserved |
| 18:16 | CLSTR0_DEF_CORE_NUM | R | 2h | Number of cores in cluster 001 - Single Core 010 - Dual Core 100 - Quad Core Reset Source: mod_g_rst_n |
| 15:8 | CLSTR0_DEF_DSP_CORE_TYPE | R | FFh | DSP core type configuration Field values (others are reserved): 8'h00 - C7x 8'h01 - C6x 8'h10 - AC7x 8'hFF - Not DSP Reset Source: mod_g_rst_n |
| 7:0 | CLSTR0_DEF_ARM_CORE_TYPE | R | 10h | ARM core type configuration Field values (others are reserved): 8'h00 - A53 8'h01 - A57 8'h10 - R5 8'h11 - M4F 8'hFF - Not ARM Reset Source: mod_g_rst_n |