SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the periodic interval after which an ASYNC packet is exported over ATB interface. This counter register controls the interval between synchronization packets. The number of bytes between which a sync packet is sent based on this counter value. Writing a value of 0x0 disables the synchronization counter, however if the client has any other synchronization scheme, that will continue to operate. When this register is written, STPMI2ATB will immediately perform synchronization and reset the counter value to the newly programmed value ensuring subsequent synchronization occurs in the period programmed. This async requests will result in a Master switch. A async request will result in async packet followed by VERSION packet which is followed by a new M8/C8 packet before any Dx packet is sent.
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| Instance Name | Physical Address |
|---|---|
| C7X256V1_DEBUG | 0007 3804 0110h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RSVD | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RSVD | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSVD | MODE | COUNT | |||||
| R | R/W | R/W | |||||
| 0h | 1h | 780h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COUNT | |||||||
| R/W | |||||||
| 780h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:13 | RSVD | R | 0h | reserved |
| 12 | MODE | R/W | 1h | Sync Count Mode: 1 indicates SYNC is 2N bytes N being derived from 11:7, value being between 12 and 27 inclusive 0 indicates N, where N is number of bytes between the ASYNC packets Counter = 2^ N, where [N = 2^m, m=11:7, 12 and 27 inclusive] (mode =1) Counter = N, where [N = 11:0] (mode =0) |
| 11:0 | COUNT | R/W | 780h | Period Count: Counts the number of bytes between Synchronization packets. |