SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the control and status settings for STP Trace control register. MID_Fifofull indicates status of internal Master/Channel Fifo as full. Data_Fifofull indicates the status of internal Data Fifo as full. It is possible that if MID_Fifofull is full and when new master_id is seen on STPMI i/f, the data will not be accepted as MID is full. It will wait for MID to be read out corresponding to Data.
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| Instance Name | Physical Address |
|---|---|
| C7X256V1_DEBUG | 0007 3804 0100h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RSVD3 | MID_FIFO_FUL | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| DATA_FIFO_FULL | RSVD2 | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSVD2 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD2 | COMPEN | RSVD1 | SNCEN | TSEN | RSVD0 | ||
| R | R/W | R | R | R/W | R | ||
| 0h | 0h | 0h | 1h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RSVD3 | R | 0h | reserved |
| 24 | MID_FIFO_FUL | R | 0h | '1' indicates STPMI2ATB internal MID packet fifo is full |
| 23 | DATA_FIFO_FULL | R | 0h | '1' indicates STPMI2ATB internal Data packet fifo is full |
| 22:6 | RSVD2 | R | 0h | reserved |
| 5 | COMPEN | R/W | 0h | Compression Enable: '1' Enables compression of data. '0' disables data compress. |
| 4:3 | RSVD1 | R | 0h | reserved |
| 2 | SNCEN | R | 1h | ASYNC Enable: 1 indicates STPASYNC is supported. 0 indicates STPASYNC is not supported. |
| 1 | TSEN | R/W | 0h | Timestamp Enable: 1 enables Timestamp. 0 disables Timestamp (it includes only a nibble TS, when disabled and a time-stamp is indicated on STPMI interface). This bit is static and should not be changed dynamically. This should be changed before client is enabled. The first TS packet sent out after ASYNC export will have either 64/48 (based on TSMAXWIDTH) bit timestamp and followed by only 4 bit Timestamp for TS packets. |
| 0 | RSVD0 | R | 0h | reserved |