SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Timer Interval Register 0. Interval match value for timer 0 in CTSET Timer Interval Register 1. Interval match value for timer 1 in CTSET Timer Interval Register 2. Interval match value for timer 2 in CTSET Timer Interval Register 3. Interval match value for timer 3 in CTSET Timer Interval Register 4. Interval match value for timer 4 in CTSET Timer Interval Register 5. Interval match value for timer 5 in CTSET Timer Interval Register 6. Interval match value for timer 6 in CTSET Timer Interval Register 7. Interval match value for timer 7 in CTSET Timer Interval Register 8. Interval match value for timer 8 in CTSET Timer Interval Register 9. Interval match value for timer 9 in CTSET Timer Interval Register 10. Interval match value for timer 10 in CTSET Timer Interval Register 11. Interval match value for timer 11 in CTSET Timer Interval Register 12. Interval match value for timer 12 in CTSET Timer Interval Register 13. Interval match value for timer 13 in CTSET Timer Interval Register 14. Interval match value for timer 14 in CTSET Timer Interval Register 15. Interval match value for timer 15 in CTSET Counter Timer Debug Event Register 0
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| Instance Name | Physical Address |
|---|---|
| C7X256V1_DEBUG | 0007 3800 88A0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INPSEL | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED | R | 0h | Reserved, returns 0 |
| 7:0 | INPSEL | R/W | 0h | Counter Timer input selection |