SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Counter Timer Control
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| Instance Name | Physical Address |
|---|---|
| C7X256V1_DEBUG | 0007 3800 8800h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| NUMSTM | NUMINPT | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| NUMINPT | NUMTIMR | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| NUMTIMR | NUMCNTR | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NUMCNTR | REVID | RESERVED | RESERVED | NUMCOREMD | |||
| R | R | NONE | R | R | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:26 | NUMSTM | R | 0h | Number of counters that can export via STM |
| 25:18 | NUMINPT | R | 0h | Number of event input signals |
| 17:13 | NUMTIMR | R | 0h | Number of timers in the module |
| 12:7 | NUMCNTR | R | 0h | Number of counters in the module |
| 6:3 | REVID | R | 0h | Revision ID of CTSET |
| 2 | RESERVED | NONE | 0h | Reserved |
| 1 | RESERVED | R | 0h | Reserved, returns 0 |
| 0 | NUMCOREMD | R | 0h | Indicated the number of mode bus interfaces, 0 is 2 CPU buses, 1 is 4 buses |