SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
CLEC event flags
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| Instance Name | Physical Address |
|---|---|
| C7X256V1_CLEC | 7D20 A000h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EVNTFR | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| EVNTFR | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| EVNTFR | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EVNTFR | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | EVNTFR | R | 0h | event flag register, read only pending status of all events regardless of they are enabled or disabled, for pulse events this flag is cleared as soon as event is sent, for level events this flag is cleared when input event is deasserted, writing 1 to ECR_n register also clears this bit in case of pending pulse event, description in spec section 4.2.2 Reset Source: mod_g_rst_n |