SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Fail Status Count Register
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_PBIST | 0036 0198h |
| C7X256V1_PBIST | 0037 0198h |
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 48 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RESERVED | FSRC1 | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | FSRC0 | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 63:36 | RESERVED | NONE | 0h | Reserved |
| 35:32 | FSRC1 | R | 0h | Fail Status Count - Port 1 (FSRC1) Reset Source: mod_g_rst_n |
| 31:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | FSRC0 | R | 0h | Fail Status Count - Port 0 (FSRC0) Reset Source: mod_g_rst_n |