SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Datalogger Register
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| C7X256V0_PBIST | 0036 0164h |
| C7X256V1_PBIST | 0037 0164h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| BRP | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | DLR1_RTM | DLR1_GNG | DLR1_MISR | ||||
| NONE | R/W | R/W | R/W | ||||
| 0h | 0h | 1h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DLR0_TSM | DLR0_CFMM | DLR0_ECAM | DLR0_CAM | DLR0_TCK | DLR0_ROM | DLR0_IDDQ | DLR0_DCM |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 1h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | RESERVED | NONE | 0h | Reserved |
| 23:16 | BRP | R/W | 0h | Datalogger 2 (BRP) Reset Source: mod_g_rst_n |
| 15:11 | RESERVED | NONE | 0h | Reserved |
| 10 | DLR1_RTM | R/W | 0h | Retention testing mode Reset Source: mod_g_rst_n |
| 9 | DLR1_GNG | R/W | 1h | GO / NO-GO testing mode Reset Source: mod_g_rst_n |
| 8 | DLR1_MISR | R/W | 0h | MISR testing mode (mainly for ROM testing) Reset Source: mod_g_rst_n |
| 7 | DLR0_TSM | R/W | 0h | Time stamp mode Reset Source: mod_g_rst_n |
| 6 | DLR0_CFMM | R/W | 0h | Column Fail Masking mode Reset Source: mod_g_rst_n |
| 5 | DLR0_ECAM | R/W | 0h | Emulation cache access mode Reset Source: mod_g_rst_n |
| 4 | DLR0_CAM | R/W | 0h | Config access mode Reset Source: mod_g_rst_n |
| 3 | DLR0_TCK | R/W | 1h | TCK Gated mode Reset Source: mod_g_rst_n |
| 2 | DLR0_ROM | R/W | 0h | ROM-based testing mode Reset Source: mod_g_rst_n |
| 1 | DLR0_IDDQ | R/W | 0h | IDDQ testing mode Reset Source: mod_g_rst_n |
| 0 | DLR0_DCM | R/W | 0h | Distributed Compare mode Reset Source: mod_g_rst_n |