SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Module Ownership Control and Status Register
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3404 0008h |
| C7X256V1_DEBUG | 0007 3804 0008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RSVD | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RSVD | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSVD | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD | OWN | CLAIM | |||||
| R | R | R/W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:3 | RSVD | R | 0h | rsvd Reset Source: cfg_rst_n |
| 2:1 | OWN | R | 0h | own status bit Reset Source: cfg_rst_n |
| 0 | CLAIM | R/W | 0h | claim control bit Reset Source: cfg_rst_n |