SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
CTSET status register
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 8014h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | HWFIFOEMPTY | ||||||
| R | R | ||||||
| 0h | 1h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESETDONE | ||||||
| R | R | ||||||
| 0h | 1h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:9 | RESERVED1 | R | 0h | Reserved, returns 0 |
| 8 | HWFIFOEMPTY | R | 1h | System Event Trace FIFO status, 1 is empty, 0 means captured data not yet exported |
| 7:1 | RESERVED | R | 0h | Reserved, returns 0 |
| 0 | RESETDONE | R | 1h | Reset status, 0 means reset ongoing, 1 indicates completed |