SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Debug Status Register This register provides all the required system state to the debug tools.
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 0014h |
| C7X256V1_DEBUG | 0007 3800 0014h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_4 | STAT_READY | STAT_EXT_RUN_SEEN | STAT_EXT_HALT_SEEN | STAT_EXT_ENABLE | STAT_IDS | RESERVED_3 | |
| R/W | R/W | R/W | R/W | R | R | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESET_OCC | RESET_ACTIVE | CLOCK_ACTIVE | IDLE_ACTIVE | STAT_NIPERM | STAT_IPERM | STAT_PRIV_HPI | STAT_PRIV_DBGM |
| R/W | R | R/W | R | R | R | R | R |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| HALT_IN_IDS | HALT_AETBP | HALT_EXT_HALT | HALT_USER | HALT_STEP | HALT_CPU_RESET | HALT_HWBP | HALT_SWBP |
| R | R | R | R | R | R | R | R |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_2 | CANCEL_IAP | CANCEL_EXE | RESTART | RESERVED | EXE_STAT | NEW_HALT | |
| R/W | R/W | R/W | R/W | R/W | R | R | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | RESERVED_4 | R/W | 0h | reserved |
| 29 | STAT_READY | R/W | 0h | Ready Status Continuously Inactive [sticky] This bit indicates the ready status of the CPU and is used to detect a CPU hang condition It is a sticky bit A simultaneous set and clear condition causes the bit to be set |
| 28 | STAT_EXT_RUN_SEEN | R/W | 0h | External Run Trigger Status This bit indicates that a qualified external run trigger was detected since the last time it was cleared It is a sticky bit A simultaneous set and clear condition causes the bit to be set |
| 27 | STAT_EXT_HALT_SEEN | R/W | 0h | External Halt Trigger Status This bit indicates that a qualified external halt trigger was detected since the last time it was cleared It is a sticky bit A simultaneous set and clear condition causes the bit to be set |
| 26 | STAT_EXT_ENABLE | R | 0h | External Debug Enable Qualifier Status This bit indicates the state of the external debug enable qualifier |
| 25 | STAT_IDS | R | 0h | State of the Interrupt During Suspend CPU State This bit indicates that an interrupt during suspend [IDS] is being serviced by the CPU |
| 24 | RESERVED_3 | R/W | 0h | reserved |
| 23 | RESET_OCC | R/W | 0h | CPU Reset Occurred [sticky] This bit is used to determine if the CPU reset has been active at least one clock since the last time it was cleared This is a sticky bit A simultaneous set and clear condition causes the bit to be set NOTE: This register has no reset value, instead it is affected by the occurrence of a CPU reset |
| 22 | RESET_ACTIVE | R | 0h | CPU Reset Status This bit indicates the reset state of the CPU core |
| 21 | CLOCK_ACTIVE | R/W | 0h | CPU Clocks Active [sticky] This is a sticky bit which is set when a rising edge is seen on the CPUs functional clock This is a sticky bit A simultaneous set and clear condition causes the bit to be set |
| 20 | IDLE_ACTIVE | R | 0h | CPU is IDLE This bit indicates the idle state of the CPU core |
| 19 | STAT_NIPERM | R | 0h | State of Non-Invasive Permissions This bit indicates whether the next execute packet has Non-Invasive Permissions It is used to detect that the CPU is executing code that is not allotted Non-Invasive Debug Permissions |
| 18 | STAT_IPERM | R | 0h | State of Invasive Permissions This bit indicates whether the next execute packet has Invasive Permissions It is used to detect that the CPU is executing secure code and can not be debugged |
| 17 | STAT_PRIV_HPI | R | 0h | State of the HPI Privilege Window This bit indicates that a high priority interrupt has been taken but has not yet been completed |
| 16 | STAT_PRIV_DBGM | R | 0h | State of the DBGM Privilege Window This bit reflects the state of the DBGM privilege window |
| 15 | HALT_IN_IDS | R | 0h | Execution Halted within an Interrupt During Suspend [IDS] This bit indicates that the CPU has halted while executing an IDS |
| 14 | HALT_AETBP | R | 0h | Execution Halted Due to an AET generated breakpoint This bit indicates that an AET-generated breakpoint has halted code execution |
| 13 | HALT_EXT_HALT | R | 0h | Execution Halted Due to an external debug halt request |
| 12 | HALT_USER | R | 0h | Execution Halted Due to a application update of the HALT bit |
| 11 | HALT_STEP | R | 0h | Execution Halted Due to a Single Step This bit indicates that the halt occurred due to the completion of a single step operation |
| 10 | HALT_CPU_RESET | R | 0h | Execution Halted Due to CPU Reset or a halt request made during CPU Reset |
| 9 | HALT_HWBP | R | 0h | Execution Halted Due to a Hardware Breakpoint This bit indicates that the halt occurred due to the detection of a hardware breakpoint |
| 8 | HALT_SWBP | R | 0h | Execution Halted Due to a SWBP This bit indicates that the halt occurred due to a software breakpoint being detected |
| 7:6 | RESERVED_2 | R/W | 0h | reserved |
| 5 | CANCEL_IAP | R/W | 0h | Indirect Access Port Request Canceled This bit indicates that an IAP read or write request has been canceled [eg due to Port Reset, CPU Reset, New debug context] since the last time it was cleared It is a sticky bit A simultaneous set and clear condition causes the bit to be set |
| 4 | CANCEL_EXE | R/W | 0h | Debug Command Request Canceled This bit indicates that a debug request has been canceled [by a NEW_HALT or by DBG_CNTL:CANCEL_EXE while a previously issued command was pending] since the last time it was cleared It is a sticky bit A simultaneous set and clear condition causes the bit to be set |
| 3 | RESTART | R/W | 0h | Execution Restart This bit indicates that the core execution resumed due to a debug command since the last time it was cleared It is a sticky bit A simultaneous set and clear condition causes the bit to be set |
| 2 | RESERVED | R/W | 0h | reserved |
| 1 | EXE_STAT | R | 0h | Execution State This bit indicates the execution status of the CPU |
| 0 | NEW_HALT | R | 0h | Debug Context Status This bit indicates that the processor has halted at a new location [or debug context] relative to the previously active debug location |