SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The SW can determine status of wrt and rd access along with other status from the ON domain
This register is located in the CORE domain and provides the control and status of the MMR Sync state machine. The RELOAD_FROM_BBD bit directly controls the the MMR Sync state machine in the DIG_CORE domain and ignores the Functional Protection state machine. The RELOAD_FROM_BBD bit can be written with 1 regardless of if RTC is locked or unlocked. RTC will ignore a write of 1 to the RELOAD_FROM_BBD bit if RTC_SYNCPEND.RD_PEND is 1, or if RTC_SYNCPEND.WR_PEND is 1, or if any interrupt status bit in the RTC_IRQSTATUS_RAW_SYS register is 1.
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| Instance Name | Physical Address |
|---|---|
| WKUP_RTCSS0 | 2B1F 0068h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RELOAD_FROM_BBD | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PWR_ENABLE_ST | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WKUP_DB_ST | WRT_ERR | O32K_CLK_OBS | RD_PEND | WR_PEND | |||
| R | R/W1TC | R | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RELOAD_FROM_BBD | R/W | 0h | The reload_from_bbd allows the registers to be reloaded from the battery backed domain. This is only allowed when the battery backed domain interface state machine is idle. Writing 1 triggers the MMR Sync to read the registers from the battery backed domain. This requires RD_PEND, WR_PEND, and all interrupts' raw status to be 0 when this is written. This operation affects the RD_PEND bit. |
| 30:9 | RESERVED | NONE | 0h | Reserved |
| 8 | PWR_ENABLE_ST | R | 0h | The SW can read the state of PIMIC_ENABLE pin, this is raw state |
| 7:4 | WKUP_DB_ST | R | 0h | The SW can read the state of EXT_WAKEUP pins, this is raw state |
| 3 | WRT_ERR | R/W1TC | 0h | Write Error Condition Wrt 1 to Clr Set when SW tries to Wrt when RTL is LOCKED or Wrt when RD_PEND is set 0 Not Occurred 1 Occurred |
| 2 | O32K_CLK_OBS | R | 0h | The SW can read the state of the main 32k clock |
| 1 | RD_PEND | R/W | 0h | Status of synchronization from ON Domain after CORE reset or RELOAD_FROM_BBD 0 Completed 1 Pending or active |
| 0 | WR_PEND | R/W | 0h | Status of synchronization to ON Domain after writing to CORE Domain over VBUS 0 Completed 1 Pending or active |