SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This is the main RTC control register
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| Instance Name | Physical Address |
|---|---|
| WKUP_RTCSS0 | 2B1F 0050h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | CNT_FMODE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| UNLOCK | RESERVED | O32K_OSC_DEP_EN | RESERVED | SW_OFF | PWR_OFF_EN | ||
| R | NONE | R/W | NONE | W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | WKUP_DB_EN | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WKUP_POL | WKUP_EN | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:26 | RESERVED | NONE | 0h | Reserved |
| 25:24 | CNT_FMODE | R/W | 0h | This defines which read freeze mode is enabled, 10 = S_CNT_LSW When SW reads S_CNT_LSW it will snap S_CNT_MSW 01 = SUB_S_CNT When SW reads SUB_S_CNT it will snap S_CNT_MSW and S_CNT_LSW 00 = Disable |
| 23 | UNLOCK | R | 0h | The status of the UNLOCKED state, 1 = UnLocked 0 = Locked |
| 22 | RESERVED | NONE | 0h | Reserved |
| 21 | O32K_OSC_DEP_EN | R/W | 0h | This controls if a high to low transition dependence is required before the CORE domain can read or write the ON domain, 1 = Enable 0 = Disable |
| 20:18 | RESERVED | NONE | 0h | Reserved |
| 17 | SW_OFF | W | 0h | The SW can issue a ON_OFF event, Wrt 1 for OFF event Wrt 0 has no effect, The OFF event will occur within 31uS and relock the core |
| 16 | PWR_OFF_EN | R/W | 0h | This allows the PMIC_ENABLE to go from a ON to OFF state by SW or ON_OFF event |
| 15:12 | RESERVED | NONE | 0h | Reserved |
| 11:8 | WKUP_DB_EN | R/W | 0h | External Wakeup Debounce Enable 1 = Enable 0 = Disable |
| 7:4 | WKUP_POL | R/W | 0h | External Wakeup Polarity 1 = Active High = Active Low |
| 3:0 | WKUP_EN | R/W | 0h | External Wakeup Enable 1 = Enable 0 = Disable |