SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The PHY Control 4 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section 1.2.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 810Ch |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| RESERVED | OTAPDLYENA | RESERVED | OTAPDLYSEL | ||||
| NONE | R/W | NONE | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| OTAPDLYSEL | RESERVED | ITAPCHGWIN | ITAPDLYENA | ||||
| R/W | NONE | R/W | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| RESERVED | ITAPDLYSEL | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:21 | RESERVED | NONE | 0h | Reserved |
| 20 | OTAPDLYENA | R/W | 0h | Output Tap Delay Enable. Enables manual control of the TX clock tap delay, for clocking the final stage flops for maintaining Hold requirements on EMMC Interface. Reset Source: vbus_smod_g_rst_n |
| 19:17 | RESERVED | NONE | 0h | Reserved |
| 16:12 | OTAPDLYSEL | R/W | 0h | Output Tap Delay Select. Manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface. Reset Source: vbus_smod_g_rst_n |
| 11:10 | RESERVED | NONE | 0h | Reserved |
| 9 | ITAPCHGWIN | R/W | 0h | Input Tap Change Window. It gets asserted by the controller while changing the itapdlysel. Used to gate of the RX clock during switching the clock source while tap is changing to avoid clock glitches. Reset Source: vbus_smod_g_rst_n |
| 8 | ITAPDLYENA | R/W | 0h | Input Tap Delay Enable. This is used for the manual control of the RX clock Tap Delay in non HS200/HS400 modes. Reset Source: vbus_smod_g_rst_n |
| 7:5 | RESERVED | NONE | 0h | Reserved |
| 4:0 | ITAPDLYSEL | R/W | 0h | Input Tap Delay Select. Manual control of the RX clock Tap Delay in the non HS200/HS400 modes. Reset Source: vbus_smod_g_rst_n |