SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The PHY Control 1 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section 1.2.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 8100h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| IOMUX_ENABLE | DQ_7_4_IOMUX_EN | RESERVED | |||||
| R/W | R/W | NONE | |||||
| 1h | 0h | 204FCE5E3E25026110000000h | |||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| RESERVED | |||||||
| NONE | |||||||
| 204FCE5E3E25026110000000h | |||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | |||||||
| NONE | |||||||
| 204FCE5E3E25026110000000h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| RESERVED | |||||||
| NONE | |||||||
| 204FCE5E3E25026110000000h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | IOMUX_ENABLE | R/W | 1h | IO mux enable. Set 1 for GPIO. Set 0 for eMMC/SD Reset Source: vbus_smod_g_rst_n |
| 30 | DQ_7_4_IOMUX_EN | R/W | 0h | IO mux enable for data lines 7 through 4 when eMMC/SD is used in 4 bit mode. Set 1 for GPIO. Set 0 for eMMC/SD Reset Source: vbus_smod_g_rst_n |
| 29:0 | RESERVED | NONE | 204FCE5E3E25026110000000h | Reserved |