SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Controller Config 3 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer to its specification listed in Section 1.2. This register sets the msb fields in the Capabilities Register inside the Arasan eMMC/SD Controller.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 8018h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| RESERVED | SUPPORT1P8VDD2 | ADMA3SUPPORT | RESERVED | ||||
| NONE | R/W | R/W | NONE | ||||
| Bh | 1h | 1h | 0h | ||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| CLOCKMULTIPLIER | |||||||
| R/W | |||||||
| 0h | |||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RETUNINGMODES | TUNINGFORSDR50 | RESERVED | RETUNINGTIMERCNT | ||||
| R/W | R/W | NONE | R/W | ||||
| 0h | 0h | 0h | 4h | ||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| TYPE4SUPPORT | DDRIVERSUPPORT | CDRIVERSUPPORT | ADRIVERSUPPORT | RESERVED | DDR50SUPPORT | SDR104SUPPORT | SDR50SUPPORT |
| R/W | R/W | R/W | R/W | NONE | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 1h | 1h | 1h | 1h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:29 | RESERVED | NONE | Bh | Reserved |
| 28 | SUPPORT1P8VDD2 | R/W | 1h | 1.8V VDD2 Support. Reset Source: vbus_smod_g_rst_n |
| 27 | ADMA3SUPPORT | R/W | 1h | ADMA3 Support. Reset Source: vbus_smod_g_rst_n |
| 26:24 | RESERVED | NONE | 0h | Reserved |
| 23:16 | CLOCKMULTIPLIER | R/W | 0h | Clock Multiplier. This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator. FFh Clock Multiplier M = 256, ...., 02h Clock Multiplier M = 3, 01h Clock Multiplier M = 2, 00h Clock Multiplier is Not Supported. Reset Source: vbus_smod_g_rst_n |
| 15:14 | RETUNINGMODES | R/W | 0h | Re-Tuning Modes. Should be set to 2'b00 as the Core supports only the Software Timer based Re-Tuning. Reset Source: vbus_smod_g_rst_n |
| 13 | TUNINGFORSDR50 | R/W | 0h | Use Tuning for SDR50. This bit should be set if the Application wants Tuning be used for SDR50 Modes. The Core operates with or with out tuning for SDR50 mode as long as the Clock can be manually tuned using tap delay. Reset Source: vbus_smod_g_rst_n |
| 12 | RESERVED | NONE | 0h | Reserved |
| 11:8 | RETUNINGTIMERCNT | R/W | 4h | Timer Count for Re-Tuning. This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. Reset Source: vbus_smod_g_rst_n |
| 7 | TYPE4SUPPORT | R/W | 0h | Driver Type 4 Support. This bit should be set based on whether Driver Type 4 for 1.8 Signalling is supported or not. Reset Source: vbus_smod_g_rst_n |
| 6 | DDRIVERSUPPORT | R/W | 0h | Driver Type D Support. This bit should be set based on whether Driver Type D for 1.8 Signalling is supported or not. Reset Source: vbus_smod_g_rst_n |
| 5 | CDRIVERSUPPORT | R/W | 0h | Driver Type C Support. This bit should be set based on whether Driver Type C for 1.8 Signalling is supported or not. Reset Source: vbus_smod_g_rst_n |
| 4 | ADRIVERSUPPORT | R/W | 0h | Driver Type A Support. This bit should be set based on whether Driver Type A for 1.8 Signalling is supported or not. Reset Source: vbus_smod_g_rst_n |
| 3 | RESERVED | NONE | 1h | Reserved |
| 2 | DDR50SUPPORT | R/W | 1h | DDR50 Support. Suggested Value is 1'b1 (The Core supports DDR50 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support DDR50. Reset Source: vbus_smod_g_rst_n |
| 1 | SDR104SUPPORT | R/W | 1h | SDR104 Support. Suggested Value is 1'b1 (The Core supports SDR104 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support SDR104. Reset Source: vbus_smod_g_rst_n |
| 0 | SDR50SUPPORT | R/W | 1h | SDR50 Support. Suggested Value is 1'b1 (The Core supports SDR50 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support SDR50. Reset Source: vbus_smod_g_rst_n |