SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Controller Config 1 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer to its specification listed in Section 1.2.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 8010h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| RESERVED | TUNINGCOUNT | ||||||
| NONE | R/W | ||||||
| 0h | 20h | ||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| RESERVED | ASYNCWKUPENA | RESERVED | |||||
| NONE | R/W | NONE | |||||
| 0h | 1h | 1h | |||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| CQFMUL | RESERVED | CQFVAL | |||||
| R/W | NONE | R/W | |||||
| 3h | 0h | c8h | |||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| CQFVAL | |||||||
| R/W | |||||||
| c8h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | RESERVED | NONE | 0h | Reserved |
| 29:24 | TUNINGCOUNT | R/W | 20h | Configures the Number of Taps (Phases) of the RX clock that is supported. The Tuning State machine uses this information to select one of the Taps (Phases) of the RX clock during the Tuning Procedure. Reset Source: vbus_smod_g_rst_n |
| 23:21 | RESERVED | NONE | 0h | Reserved |
| 20 | ASYNCWKUPENA | R/W | 1h | Determines the Wakeup Signal Generation Mode. 0: Synchronous Wakeup Mode: The xin_clk has to be running for this mode. The Card Insertion/Removal/Interrupt events are detected synchronously on the xin_clk and the Wakeup Event is generated. The Assertion and deassertion of the wakeup Event signal synchronous to xin_clk. 1: Asyncrhonous Wakeup Mode: The xin_clk and the host_clk can be stopped in this mode and the Wake up Event is asynchronously generated based on the Card Insertion/Removal/Interrupt Events. The Assertion and deassertion of the wakeup Event signal is asynchronous. Reset Source: vbus_smod_g_rst_n |
| 19:16 | RESERVED | NONE | 1h | Reserved |
| 15:12 | CQFMUL | R/W | 3h | FMUL for the CQ Internal Timer Clock Frequency Reset Source: vbus_smod_g_rst_n |
| 11:10 | RESERVED | NONE | 0h | Reserved |
| 9:0 | CQFVAL | R/W | c8h | FVAL for the CQ Internal Timer Clock Frequency Reset Source: vbus_smod_g_rst_n |