SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is updated by CQE when an error occurs on data or command related to a task activity. When such error is detected by CQE or indicated by the eMMC controller CQE stores in CQTERRI the task IDs and the command indices of the commands which were executed on the 343 command line and data lines when the error occurred.Software is expected to use this information in the error recovery procedure.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0254h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| DATERR_VALID | RESERVED | DATERR_TASK_ID | |||||
| R | NONE | R | |||||
| 0h | 0h | 0h | |||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| RESERVED | DATERR_CMD_INDEX | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESP_MODE_VALID | RESERVED | RESP_MODE_TASK_ID | |||||
| R | NONE | R | |||||
| 0h | 0h | 0h | |||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| RESERVED | RESP_MODE_CMD_INDEX | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | DATERR_VALID | R | 0h | Data Transfer Error Fields Valid This bit is updated when an error is detected by CQE, or indicated by eMMC controller. If a data transfer is in progress when the error is detected/indicated, the bit is set to 1. If a no data transfer is in progress when the error is detected/indicated, the bit is cleared to 0. Reset Source: vbus_amod_g_rst_n |
| 30:29 | RESERVED | NONE | 0h | Reserved |
| 28:24 | DATERR_TASK_ID | R | 0h | Data Transfer Error Task ID This field indicates the ID of the task which was executed on the data lines when an error occurred. The field is updated if a data transfer is in progress when an error is detected by CQE, or indicated by eMMC controller Reset Source: vbus_amod_g_rst_n |
| 23:22 | RESERVED | NONE | 0h | Reserved |
| 21:16 | DATERR_CMD_INDEX | R | 0h | Data Transfer Error Command Index This field indicates the index of the command which was executed on the data lines when an error occurred. The index shall be set to EXECUTE_READ_TASK[CMD46] or EXECUTE_WRITE_TASK [CMD47] accord-ing to the data direction. The field is updated if a data transfer is in progress when an error is detected by CQE, or indicated by eMMC controller. Reset Source: vbus_amod_g_rst_n |
| 15 | RESP_MODE_VALID | R | 0h | Response Mode Error Fields Valid This bit is updated when an error is detected by CQE, or indicated by eMMC controller. If a command transaction is in progress when the error is detected/indicated, the bit is set to 1. If a no command transaction is in progress when the error is detected/indicated, the bit is cleared to 0. Reset Source: vbus_amod_g_rst_n |
| 14:13 | RESERVED | NONE | 0h | Reserved |
| 12:8 | RESP_MODE_TASK_ID | R | 0h | Response Mode Error Task ID This field indicates the ID of the task which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is detected by CQE, or indicated by eMMC controller. Reset Source: vbus_amod_g_rst_n |
| 7:6 | RESERVED | NONE | 0h | Reserved |
| 5:0 | RESP_MODE_CMD_INDEX | R | 0h | Response Mode Error Command Index This field indicates the index of the command which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is detected by CQE, or indicated by eMMC controller. Reset Source: vbus_amod_g_rst_n |