SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used for removing an outstanding task in the CQE. 327. The register should be used only when CQE is in Halt state.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0238h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| CQTCLR | |||||||
| R/W | |||||||
| 0h | |||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| CQTCLR | |||||||
| R/W | |||||||
| 0h | |||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| CQTCLR | |||||||
| R/W | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| CQTCLR | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | CQTCLR | R/W | 0h | Writing 1 to bit n of this register orders CQE to clear a task which software has previously issued.This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit.When software writes 1 to a bit in this register,CQE updates the value to 1, and starts clearing the data structures related to the task. CQE clears the bit fields [sets a value of 0] in CQTCLR and in CQTDBR once clear operation is complete.Software should poll on the CQTCLR until it is cleared to verify clear operation was complete.Writing to this register only clears the task in the CQE and does not have impact on the device. In order to dis-card the task in the device, host software shall send CMDQ_TASK _MGMT while CQE is still in Halt state.Host driver is not allowed to use this register to clear multiple tasks at the same time. Clearing multiple tasks can be done using CQCTL register.Writing 0 to a register bit shall have no impact. Reset Source: vbus_amod_g_rst_n |