SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register indicates to software which tasks are queued in the device, awaiting execution.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0234h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| CQDP_TSKS | |||||||
| R | |||||||
| 0h | |||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| CQDP_TSKS | |||||||
| R | |||||||
| 0h | |||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| CQDP_TSKS | |||||||
| R | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| CQDP_TSKS | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | CQDP_TSKS | R | 0h | Bit n of this register is set if and only if QUEUED_TASK_PARAMS [CMD44] and QUEUED_TASK_ADDRESS [CMD45] were sent for this specific task and if this task hasnt been executed yet.CQE shall set this bit after receiving a successful response for CMD45. CQE shall clear this bit after the task has completed execution.Software needs to read this register in the task-discard procedure, when the controller is halted, to determine if the task is queued in the device. If the task is queued,the driver sends a CMDQ_TASK_MGMT [CMD48] to the device ordering it to discard the task. Then software clears the task in the CQE. Only then the software orders CQE to resume its operation using CQCTL register. Reset Source: vbus_amod_g_rst_n |