SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Using this register, software triggers CQE to process a new task.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0228h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| CQTDB_VAL | |||||||
| R/W1TS | |||||||
| 0h | |||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| CQTDB_VAL | |||||||
| R/W1TS | |||||||
| 0h | |||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| CQTDB_VAL | |||||||
| R/W1TS | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| CQTDB_VAL | |||||||
| R/W1TS | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | CQTDB_VAL | R/W1TS | 0h | Command Queueing Task Doorbell Software shall configure TDLBA and TDLBAU, and enable CQE in CQCFG before using this register. Writing 1 to bit n of this register triggers CQE to start pro-cessing the task encoded in slot n of the TDL. CQE always processes tasks in-order according to the order submitted to the list by CQTDBR write transac-tions. CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS[CMD44] and QUEUED_TASK_ADDRESS [CMD45]commands to the device. CQE processes DCMD tasks [in slot #31, when enabled]by reading the Task Descriptor, and generating the com-mand encoded by its index and argument. The corresponding bit is cleared to 0 by CQE in one of the following events: [a] When a task execution is completed [with success or error] [b] The task is cleared using CQTCLR register [c] All tasks are cleared using CQCTL register [d] CQE is disabled using CQCFG register Software may initiate multiple tasks at the same time [batch submission] by writing 1 to multiple bits of this register in the same transaction. In the case of batch submission: CQE shall process the tasks in order of the task index,starting with the lowest index. If one or more tasks in the batch are marked with QBR,the ordering of execution will be based on said process-ing order. Writing 0 by software shall have no impact on the hard-ware, and will not change the value of the register bit. Reset Source: vbus_amod_g_rst_n |