SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register controls the interrupt coalescing feature.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 021Ch |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| CQINTCOALESC_ENABLE | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| RESERVED | IC_STATUS | RESERVED | |||||
| NONE | R | NONE | |||||
| 0h | 0h | 0h | |||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | CTR_THRESHOLD | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| RESERVED | TIMEOUT_VAL | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | CQINTCOALESC_ENABLE | R/W | 0h | When set to 0 by software, command responses are neither counted nor timed. Interrupts are still triggered by completion of tasks with INT=1 in the Task Descriptor. When set to 1, the interrupt coalescing mechanism is enabled and coalesced interrupts are generated. Reset Source: vbus_amod_g_rst_n |
| 30:21 | RESERVED | NONE | 0h | Reserved |
| 20 | IC_STATUS | R | 0h | This bit indicates to software whether any tasks [with INT=0] have completed and counted towards interrupt coalescing [i.e., ICSB is set if and only if IC counter > 0]. Bit Value Description 1 = At least one task completion has been counted [IC counter >0] 0 = No task completions have occurred since last counter reset [IC counter =0] Reset Source: vbus_amod_g_rst_n |
| 19:13 | RESERVED | NONE | 0h | Reserved |
| 12:8 | CTR_THRESHOLD | R/W | 0h | Interrupt Coalescing Counter Threshold [ICCTH]: Software uses this field to configure the number of task completions [only tasks with INT=0 in the Task Descriptor] which are required in order to generate an interrupt. Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. The counter is reset by software during the interrupt service routine. The counter stops counting when it reaches the value configured in ICCTH. The maximum allowed value is 31 NOTE : When ICCTH is 0, task completions are not counted, and counting-based interrupts are not generated.In order to write to this field, the ICCTHWEN bit must be set at the same write operation. Reset Source: vbus_amod_g_rst_n |
| 7 | RESERVED | NONE | 0h | Reserved |
| 6:0 | TIMEOUT_VAL | R/W | 0h | Interrupt Coalescing Timeout Value [ICTOVAL]: Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. Timer Operation: The timer is reset by software during the interrupt service routine. It starts running when a data transfer task with INT=0 is completed, after the timer was reset. When the timer reaches the value configured in ICTOVAL field it generates an interrupt and stops. The timers unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register.The minimum value is 01h [1024 clock periods] and the maximum value is 7Fh [127*1024 clock periods]. For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency [period = 52.08 ns]. If the setting in ICTOVAL is 10h, the calculated polling period is 16*1024*52.08 ns= 853.33 us NOTE: When ICTOVAL is 0, the timer is not running, and timer-based interrupts are not generated. In order to write to this field, the ICTOVALWEN bit must be set at the same write operation. Reset Source: vbus_amod_g_rst_n |