SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register enables and disables the generation of interrupts to host software. When a bit is set 304 ( 1 ) and the corresponding bit in CQIS is set, then an interrupt is gene -rated. Interrupt sources 305 that are disabled ( 0 ) are still indicated in the CQIS register. This register is bit-index matched 306 to CQIS register.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0218h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| RESERVED | TASK_ERROR | TASK_CLEARED | RESP_ERR_DET | TASK_COMPLETE | HALT_COMPLETE | ||
| NONE | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:5 | RESERVED | NONE | 0h | Reserved |
| 4 | TASK_ERROR | R/W | 0h |
Task Error Interrupt Signal Enable [TERR]
When set and CQIS.TERR is asserted, the CQE shall generate an interrupt
1 0 |
| 3 | TASK_CLEARED | R/W | 0h |
Task Cleared Signal Enable [TCL]
When set and CQIS.TCL is asserted, the CQE shall generate an interrupt
1 0 |
| 2 | RESP_ERR_DET | R/W | 0h |
Response Error Detected Signal Enable [TCC]
When set and CQIS.RED is asserted, the CQE shall generate an interrupt
1 0 |
| 1 | TASK_COMPLETE | R/W | 0h |
Task Complete Signal Enable [TCC]
When set and CQIS.TCC is asserted, the CQE shall generate an interrupt
1 0 |
| 0 | HALT_COMPLETE | R/W | 0h |
Halt Complete Signal Enable [HAC]
When set and CQIS.HAC is asserted, the CQE shall generate an interrupt
1 0 |