SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register indicates pending interrupts that require service. Each bit in this registers is asserted 296 in response a specific event, only if the respective bit is set in CQ ISTE register.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0210h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| RESERVED | TASK_ERROR | TASK_CLEARED | RESP_ERR_DET | TASK_COMPLETE | HALT_COMPLETE | ||
| NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:5 | RESERVED | NONE | 0h | Reserved |
| 4 | TASK_ERROR | R/W1TC | 0h |
Task Error Interrupt [TERR] This bit is asserted when task error is detected due to invalid task descriptor
1 Task Error interrupt is generated 0 No Interrupt |
| 3 | TASK_CLEARED | R/W1TC | 0h |
Task Cleared [TCL] This status bit is asserted [if CQISTE.TCL=1] when a task clear operation is completed by CQE. The com-pleted task clear operation is either an individual task
clear [CQTCLR] or clearing of all tasks [CQCTL].
1 Task clear interrupt is generated 0 No Interrupt |
| 2 | RESP_ERR_DET | R/W1TC | 0h | Response Error Detected Interrupt [RED] This status bit is asserted [if CQISTE.RED=1] when a response is received with an error bit set in the device status field. The contents of the device status field are listed in Section 6.13.Software uses CQRMEM register to configure which device status bit fields may trigger an interrupt, and which are masked. Reset Source: vbus_amod_g_rst_n |
| 1 | TASK_COMPLETE | R/W1TC | 0h |
Task Complete Interrupt [TCC] This status bit is asserted [if CQISTE.TCC=1] when atleast one of the following two conditions are met:
[1] A task is completed and the INT bit is set in its Task Descriptor
[2] Interrupt caused by Interrupt Coalescing logic [see Section C.4.9]
1 Task complete interrupt is generated 0 No Interrupt |
| 0 | HALT_COMPLETE | R/W1TC | 0h |
Halt Complete Interrupt [HAC] This status bit is asserted [if CQISTE.HAC=1] when halt bit in CQCTL register transitions from 0 to 1 indicating
that host controller has completed its current ongoing task and has entered halt state.
1 Halt complete interrupt is generated 0 No Interrupt |