SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 020Ch |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | CLEAR_ALL_TASKS | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| RESERVED | HALT_BIT | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:9 | RESERVED | NONE | 0h | Reserved |
| 8 | CLEAR_ALL_TASKS | R/W | 0h | Clear All Tasks Software shall write 1 this bit when it wants to clear all the tasks sent to the device. This bit can only be written when CQE is in halt state [i.e.Halt bit is 1]. When software writes 1, the value of the register is updated to 1, and CQE shall reset CQTDBR register and all other context information for all unfinished tasks. Then CQE will clear this bit.Software should poll on this bit until it is set to back 0 and may then resume normal operation, by clearing the Halt bit. CQE does not communicate to the device that the tasks were cleared. It is softwares responsibility to order the device to discard the tasks in its queue using CMDQ_TASK_MGMT command. Writing 0 to this register shall have no effect. Reset Source: vbus_amod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | HALT_BIT | R/W | 0h | Halt Host software shall write 1 to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus. For example, issuing a Discard Task command [CMDQ_TASK_MGMT] When software writes 1, CQE shall complete the ongo-ing task if such a task is in progress. Once the task is completed and CQE is in idle state,CQE shall not issue new commands and shall indicate so to software by setting this bit to 1. Software may poll on this bit until it is set to 1, and may only then send commands on the eMMC bus. In order to exit halt state [i.e. resume CQE activity], soft-ware shall clear this bit [write 0]. Writing 0 when thevalue is already 0 shall have no effect. Reset Source: vbus_amod_g_rst_n |