SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0208h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | DCMD_ENA | RESERVED | TASK_DESC_SIZE | ||||
| NONE | R/W | NONE | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| RESERVED | CQ_ENABLE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:13 | RESERVED | NONE | 0h | Reserved |
| 12 | DCMD_ENA | R/W | 0h |
Direct Command [DCMD] Enable This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor, or a Direct Command Task Descriptor.
CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor.
Bit Value Description
1 = Task descriptor in slot #31 is a DCMD Task Descrip-tor
0 = Task descriptor in slot #31 is a Data Transfer Task Descriptor
1 0 |
| 11:9 | RESERVED | NONE | 0h | Reserved |
| 8 | TASK_DESC_SIZE | R/W | 0h |
Task Descriptor Size This bit indicates whether the task descriptor size is 128 bits or 64 bits as detailed in Data Structures section. This bit can only be configured when Command Queueing
Enable bit is 0 [command queueing is disabled] Bit Value Description
1 = Task descriptor size is 128 bits
0 = Task descriptor size is 64 bits
1 0 |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | CQ_ENABLE | R/W | 0h |
Command Queueing Enable Software shall write 1 this bit when in order to enable command queueing mode [i.e. enable CQE].
When this bit is 0, CQE is disabled and software controls the eMMC bus using the legacy eMMC host controller.
Before software writes 1 to this bit, software shall verify that the eMMC host controller is in idle state and there are no commands or data transfers ongoing.
When software wants to exit command queueing mode,it shall clear all previous tasks if such exist before setting this bit to 0.
1 Command Queueing mode is Enabled 0 Command Queueing mode is Disabled |