SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is not physically implemented, rather it is an address where UHS-II Error Interrupt Status register can be written.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0120h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| VENDOR_SPECIFIC | RESERVED | ||||||
| W | NONE | ||||||
| 0h | 0h | ||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| RESERVED | TIMEOUT_DEADLOCK | TIMEOUT_CMD_RES | |||||
| NONE | W | W | |||||
| 0h | 0h | 0h | |||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| ADMA | RESERVED | EBSY | |||||
| W | NONE | W | |||||
| 0h | 0h | 0h | |||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| UNRECOVERABLE | RESERVED | TID | FRAMING | CRC | RETRY_EXPIRED | RES_PKT | HEADER |
| W | NONE | W | W | W | W | W | W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:27 | VENDOR_SPECIFIC | W | 0h | Force Event for Vendor Specific Error 0h - Not Affected 1h - Vendor Specific Error Status is set Reset Source: vbus_amod_g_rst_n |
| 26:18 | RESERVED | NONE | 0h | Reserved |
| 17 | TIMEOUT_DEADLOCK | W | 0h | Setting this bit forces the Host Controller to set Timeout for Deadlock in the UHS-II Error Interrupt Status register.
1 Timeout for Deadlock Error status is set 0 No Interrupt |
| 16 | TIMEOUT_CMD_RES | W | 0h | Setting this bit forces the Host Controller to set Timeout for CMD_RES in the UHS-II Error Interrupt Status register.
1 Timout for CMD_RES Status is set 0 No Interrupt |
| 15 | ADMA | W | 0h | Setting this bit forces the Host Controller to set ADMA Error in the UHS-II Error Interrupt Status register.
1 ADMA error status is set 0 No Interrupt |
| 14:9 | RESERVED | NONE | 0h | Reserved |
| 8 | EBSY | W | 0h | Setting this bit forces the Host Controller to set EBSY Error in the UHS-II Error Interrupt Status register.
1 EBSY error status is set 0 No Interrupt |
| 7 | UNRECOVERABLE | W | 0h | Setting this bit forces the Host Controller to set Unrecover-able Error in the UHS-II Error Interrupt Status register.
1 Unrecoverable error status is set 0 No Interrupt |
| 6 | RESERVED | NONE | 0h | Reserved |
| 5 | TID | W | 0h | Setting this bit forces the Host Controller to set TID Error in the UHS-II Error Interrupt Status register.
1 TID error status is set 0 No Interrupt |
| 4 | FRAMING | W | 0h | Setting this bit forces the Host Controller to set Framing Error in the UHS-II Error Interrupt Status register.
1 Framing error status is set 0 No Interrupt |
| 3 | CRC | W | 0h | Setting this bit forces the Host Controller to set CRC Error in the UHS-II Error Interrupt Status register.
1 CRC error status is set 0 No Interrupt |
| 2 | RETRY_EXPIRED | W | 0h | Setting this bit forces the Host Controller to set Retry Expired in the UHS-II Error Interrupt Status register.
1 Retry expired error status is set 0 No Interrupt |
| 1 | RES_PKT | W | 0h | Setting this bit forces the Host Controller to set RES Packet Error in the UHS-II Error Interrupt Status register.
1 RES packet error status is set 0 No Interrupt |
| 0 | HEADER | W | 0h | Setting this bit forces the Host Controller to set Header Error in the UHS-II Error Interrupt Status register.
1 Header error status is set 0 No Interrupt |