SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Start Address of PHY settings is pointed by Pointer for UHS-II Setting Register.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0104h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| N_LSS_DIR | N_LSS_SYN | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| HIBERNATE_ENA | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| SPEED_RANGE | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | RESERVED | NONE | 0h | Reserved |
| 23:20 | N_LSS_DIR | R/W | 0h | The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field. 0h - 8 x16 LSS 1h - 8 x 1 LSS 2h - 8 x 2 LSS 3h - 8 x 3 LSS ...... ...... Fh - 8 x 15 LSS Reset Source: vbus_amod_g_rst_n |
| 19:16 | N_LSS_SYN | R/W | 0h | The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ...... Fh - 4 x 15 LSS Reset Source: vbus_amod_g_rst_n |
| 15 | HIBERNATE_ENA | R/W | 0h | After checking card capability of Hibernate mode, if all devices support Hibernate mode, this bit may be set. This bit determines whether Host remains in Dormant state or goes to Hibernate state. In Hibernate mode, VDD1 Power may be off.
1 Hibernate Enabled 0 Hibernate Disabled |
| 14:8 | RESERVED | NONE | 0h | Reserved |
| 7:6 | SPEED_RANGE | R/W | 0h | PLL multiplier is selected by this field.Change of PLL Multiplier is not effective immediately and is applied from exiting Dormant State.
'00' Range A [Default]
'01' Range B
'10' Reserved
'11' Reserved
3 Reserved 2 Reserved 1 Range B 0 Range A (Default) |
| 5:0 | RESERVED | NONE | 0h | Reserved |